1. Field of the Invention
The present invention relates to memory devices, in particular, semiconductor memory devices, and most particularly, scalable, power-efficient semiconductor memory devices.
2. Background of the Art
Memory structures have become integral parts of modern VLSI systems, including digital signal processing systems. Although it typically is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory system and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (SRAM), which can retain its memory state without the need for refreshing as long as power is applied to the cell. In an SRAM device, the memory state II usually stored as a voltage differential within a bistable functional element, such as an inverter loop. A SRAM cell is more complex than a counterpart dynamic RAM (DRAM) cell, requiring a greater number of constituent elements, preferably transistors. Accordingly, SRAM devices commonly consume more power and dissipate more heat than a DRAM of comparable memory density, thus efficient; lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system. Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptions of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be xe2x80x9cscalablexe2x80x9d, often fail to meet design limitations once these memory subsystem designs are scaled-up for use in a VLSI system with need for a greater memory cell population and/or density.
There is a need for an efficient, scalable, high-performance, low-power memory structure that allows a system designer to create a SRAM memory subsystem that satisfies strict constraints for device area, power, performance, noise sensitivity, and the like. Moreover, there is a need for a high speed low power data transfer bus.
The present invention satisfies the above needs by providing a high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment of the present invention, the controlled voltage swing data bus circuit, an inverter is coupled with a pass transistor, preferably pMOS, and a discharge transistor, preferably nMOS, and the combination is coupled with a data bus. The discharge transistor is preferably programmed to provide a first preselected bus operational characteristic by controlling the rate and extent of voltage decay on the data bus, which can occur when the pass transistor is ON, coupling the discharge transistor through to the data bus. The pass transistor also may be programmed to enhance the control of a bus operational characteristic. In another embodiment of the invention herein, multiple discharge transistors, again, preferably nMOS, can be coupled to the data bus via the pass transistor. In this case, it is preferred that each of the discharge transistors be selectively programmed to provide additional preselected bus operational characteristics by selectably controlling the rate and extent of voltage decay on the data bus. Advantageously, by employing multiple, programmable discharge transistors, multiple, distinct logic levels can be selectably imposed on the data bus. In addition, the availability of multilevel logic permits transferring encoded data to the data bus. Concurrently with effecting a reduction in power consumption, limited voltage swings on the data bus tends to increase the speed of the bus. Furthermore, multilevel logic signal can transmit information with fewer signal lines, relative to standard bi-level logic signals.
In another embodiment of the invention herein, a bidirectional high speed low power data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer. Again, power consumption is reduced even while increasing the speed of the bus. One preferred embodiment of the bidirectional data transfer bus couples a first data bus and a second data bus with cross-linked inverters. Interposed between each of the inverters, and its associated bus, is a respective pass transistor, preferably pMOS, with the node between the pass transistor and the inverter forming the input node for the respective bus. Also, coupled between each input node and ground, is a signal discharge transistor, preferably nMOS, which facilitates data transfer between the buses.
Furthermore, it is desirable to couple each of the inverters with a clocked charge/discharge circuit, preferably using a common clock signal, which charge/discharge circuit can precharge/discharge the input nodes, depending upon the state of the clock and the data on the associated bus. While it is preferred to program the signal discharge transistors to provide preselected bus operational characteristics, including for example, rate of voltage decay on the associated bus, additional programmed signal discharge transistors may be included in the bidirectional circuit to effect multilevel logic.
The data transfer bus circuits of the present invention can be used to couple a sense amplifier or a wordline decoder, including for example, a global sense amplifier, a local sense amplifier, a global wordline decoder, and a local wordline decoder, to a data bus.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the following drawings.